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tm data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7382 features ? accuracy up to 2.3 arc minutes internal synthesized reference +5 volt only option programmable resolution, dual bandwidth and tracking rate internal encoder emulation with independent resolution control differential resolver input mode velocity output eliminates tachometer built-in-test (bit) output, no 180 hangup -40 to +85c operating temperature description the rd-19230 is a small and versatile, low cost, state-of-the-art 16- bit monolithic resolver-to-digital converter. this single chip convert- er offers programmable features such as resolution, bandwidth, velocity output scaling and encoder emulation. resolution programming allows selection of 10, 12, 14, or 16 bit, with accuracies to 2.3 min. the parallel digital data and the internal encoder emulation signals (a q u ad b ) have independent resolution control. internal encoder emulation will permit inhibiting (freezing) the parallel digital data without interrupting the a and b outputs. the internal synthesized reference section eliminates errors due to quadrature voltage and ensures operation with a rotor-to-stator phase shift of up to 45 degrees. the velocity output (vel) can be used in place of a tachometer. it has a range of 4 v relative to analog ground. the velocity scale factor/tracking rate is programmed with a single resistor. this converter provides the option of using a second set of filter components which can be used in dual bandwidth or switch on the fly applications. applications with its low cost, small size, high accuracy, and versatile perfor- mance, the rd-19230 converter is ideal for use in modern high per- formance industrial control systems. it is ideal for users who wish to use a resolver input in their encoder based system. typical applica- tions include motor control, machine tool control, robotics, and process control. ? 1998, 1999 data device corporation rd-19230 16-bit monolithic tracking resolver-to-digital converter make sure the next card you purchase has...
2 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 figure 1. rd-19230 series block diagram sin -s +s cos -c +c vddp pcap ncap vssp agnd vdd gnd vss control transformer -5 v inverter data latch gain demodulator 16 bit up/down counter hysteresis rh rl bit vco & timing - + - + d1 d0 inh em bit 1 - bit 16 el cb/zip r clk r set r v -vco a u/b a quad b internal encoder emulation synthesized reference vel zip_en - + r b c bw c bw/ 10 c bw r b c bw/ 10 up/dn shift d1 d0 d1 d0 vel2 vel1 v e l s j 1 v e l s j 2
3 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 50 pf+ logic 0: 1 ttl load, 1.6 ma at 0.4 v max. logic 1; 10 ttl loads, -0.4 ma at 2.8 v min. logic 0; 100 mv max. driving cmos logic 1; +5 v supply minus 100 mv min. driving cmos high z; 10 a || 5 pf max. (note 8) 10, 12, 14, or 16 parallel lines; natural binary angle positive logic (see note 2) 0.25 to 0.75 s positive pulse leading edge initiates counter update. (cb functions with zip_en pin tied to +5 v or nc) logic 1 at all 0?s (zip_en pin tied to gnd) logic 0 for bit condition. the bit error is triggered if any of the following conditions exist: ~ 100 lsb?s of error, loss of signal (los), or loss of reference (lor) is less than 500 mvp, or a false null occurs when the phase detect circuitry causes a bit and corrects the error incremental encoder output logic 0 = 0.8 v max. logic 1 = 2.0 v min. loading = 10 a max p.u. cur- rent source to +5 v || 5 pf max. cmos transient protected logic 0 inhibits; data stable within 150 ns logic 0 enables; data stable within 150 ns logic 1 = high impedance; data high z within 100 ns (note 8) mode d1 d0 resolution resolver 0 0 10 bits 0 1 12 bits 1 0 14 bits 1 1 16 bits lvdt -5v 0 8 bits 0 -5v 10 bits 1 -5v 12 bits -5v -5v 14 bits logic 0 enables zip logic 1 enables cb logic 0 = 1.5 v max. logic 1 = 3.5 v min. negative voltage = -3.5 v min. logic 1 select vel1 components logic 0 select vel2 components logic 1 will increase gain by 4 logic 0 will decrease gain by 4 -5 v gain remains constant logic 0 enables encoder emulation falling edge latches encoder resolution (note 5) 45 max. from 400 hz to 10khz deg digital inputs ttl / cmos compatible inputs inhibit (inh ) enable bits 1 to 8 (em ) enable bits 9 to 16 (el ) resolution and mode control (d1 & d0) (see notes 1 & 2) zip_en cmos compatible inputs shift up /dn a q u ad b synthesized reference sig/ref phase shift correction (+s, -s, sin, +c, -c, cos) resolver, differential, groundbased 2 15% 25 continuous 10m min || 10 pf. vrms vp ? signal input type voltage: operating overload input impedance (+ref, -ref) differential 10 max. (1 min.) 5 max. (0.5 min) 25 continuous; 100 transient dc to 10k 10m min. || 20 pf 3 vp-p vp vp hz ? vp reference type voltage: differential single ended overload frequency input impedance common mode range 47-1k (4) 1k - 4k 4k - 10k 4 +1 lsb 4 +1 lsb 5 +1 lsb 2 +1 lsb 2 +1 lsb 3 +1 lsb 1 1 2 1 1 2 hz min min lsb lsb carrier frequency range accuracy -xx2 -xx3 (note 3) repeatability differential linearity 10, 12, 14, or 16 (note 1 & 2) bits resolution value unit parameter these specs apply over the rated power supply, temperature, and ref- erence frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion. table 1. rd-19230 specifications table 1. rd-19230 specifications (continued) parameter unit value digital outputs drive capability parallel data (1-16) converter busy (cb) zero index pulse (zip) built-in-test (bit ) a, b dynamic characteristics resolution tracking rate (min) bandwidth (closed loop) ka a1 a2 a b acceleration (1 lsb lag) settling time (179 step) bits rps hz 1/sec 2 1/sec 1/sec 1/sec 1/sec deg/s 2 msec (at maximum bandwidth) 10 12 14 16 1152 288 72 18 1200 1200 600 300 5.7m 5.7m 1.4m 360k 19.5 19.5 4.9 1.2 295k 295k 295k 295k 2400 2400 1200 600 1200 1200 600 300 2m 500k 30k 2k 2 8 20 50 velocity characteristics polarity voltage range (full scale) scale factor error scale factor tc reversal error linearity zero offset zero offset tc load v % ppm/c % % mv v/c k ? positive for increasing angle 4 (at nominal power supply) 10 typ 20 max 100 typ 200 max 0.75 typ 1.3 max 0.25 typ 0.50 max 5 typ 10 max 15 typ 30 max 8 max these specs apply over the rated power supply, temperature, and ref- erence frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
4 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 theory of operation the rd-19230 is a mixed signal cmos ic containing analog input and digital output sections. precision analog circuitry is merged with digital logic to form a complete high-performance tracking resolver-to-digital converter. for user flexibility and con- venience, the converter bandwidth, dynamics, and velocity scal- ing are externally set with passive components. figure 1 is the rd-19230 functional block diagram. the ana- log conversion electronics require 5 vdc power supplies, and the converter contains a charge pump to provide the user with the option of a single-ended +5 vdc supply. the converter front- end consists of differential sine and cosine input amplifiers which are protected up to 25 v with 2 k ? resistors and diode clamps to the 5 vdc supplies. by performing the following trigonomet- ric identity, sin ( cos ) - cos ( sin ) = sin( - ), the control transformer (ct) compares the analog input signals ( ) with the digital output ( ) , resulting in an error signal proportional to the sin of the angular difference. the ct uses a combination of amplifiers, switches, logic and capacitors in precision ratios to perform the calculation. note: the error output of the ct is normally sinusoidal, but in lvdt mode, it is triangular (linear) and can be used to convert any linear transducer output. the converter accuracy is limited by the precision of the com- puting elements in the ct. instead of a traditional precision resistor network, this converter uses capacitors with precisely controlled ratios. sampling techniques are used to eliminate errors due to voltage drift and op-amp offsets. the error processing is performed using the industry standard technique for type ii tracking converters. the dc error is inte- grated yielding a velocity voltage which in turn drives a voltage controlled oscillator (vco). this vco is an incremental integra- tor (constant voltage input to position rate output) which, togeth- er with the velocity integrator, forms a type ii servo feedback loop. a lead in the frequency response is introduced to stabilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. the settings of the various error processor gains and break fre- quencies are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user. table 1 notes: 1. as parallel resolution is reduced, pairs of bits are disabled. (unused bits are set to a logic ?0.?) 14 bit resolution: 15/16 disabled 12 bit resolution: 13/14, 15/16 disabled 10 bit resolution: 11/12, 13/14, 15/16 disabled 2. in lvdt mode, bit 3 is the msb and resolution is programmable to 8, 10, 12, and 14 bits. 3. accuracy in lvdt mode is 0.15% + 1 lsb of full scale. 4. in the frequency range of 47hz to 1khz, there will be 1 lsb of jitter at quadrant boundaries. 5. the maximum phase shift tolerance will degrade linearly from 45 degrees at 400 hz to 30 degrees at 60 hz. 6. when using the -5v inverter, the v dd supply current will double and v ssp can be up to 20% low, or -4v. 7. || = in parallel with. 8. high z refers to parallel data only. 9. normal esd (electro static device) handling precautions should be observed. temperature range operating -30x -20x storage junction-to-case junction-to-ambient junction temp max c c c c/w c/w c 0 to +70 -40 to +85 -65 to +150 20 50 150 power supplies nominal voltage voltage range max volt. w/o damage current v % v ma (note 6) +5 (vdd) -5 (vss) 5 5 +7 -7 25 max. (each), 17 typ.* (* typical current is when a 30k resistor is used for the current set.) oz(g) weight 0.018 ( 0.5 ) 0.52 x 0.52 (13.2 x 13.2) in(mm) physical characteristics size: 64-pin quad flat pack parameter unit value table 1. rd-19230 specifications (continued) these specs apply over the rated power supply, temperature, and ref- erence frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
5 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 transfer function and bode plot the dynamic performance of the converter can be determined from its transfer function block diagrams and bode plots (open and closed loop). these are shown in figures 2, 3, and 4. the open loop transfer function is as follows: where a is the gain coefficient and a 2 =a 1 a 2 and b is the frequency of lead compensation. 2 s a +1 ( ) b 2 s s +1 ( ) 10b open loop transfer function = gain 11 mv/lsb 16 bit up/down counter r 1 vco r v r b c bw c /10 bw vel -vco h = 1 vel sj1 vel c f s s ct + - resolver input ( ) 50 pf c vco digital output ( ) demod ?.25 v threshold 1 figure 2. transfer function block diagram #1 -12 db/oct ba 2a -6 db/oct 10b (rad/sec) 2a 2 2 a (rad/sec) f = bw (hz) = bw 2 a closed loop (b = a/2) gain = 0.4 gain = 4 (critically damped) open loop figure 4. bode plots error processor resolver input ( ) velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 + - e a 2 s figure 3. transfer function block diagram #2 the components of gain coefficient are error gradient, integrator gain, and vco gain. these can be broken down as follows: r v , r b , and c bw are selected by the user to set velocity scaling and bandwidth. - error gradient = 0.011 volts per lsb (ct + error amp + demod with 2 vrms input) - integrator gain = volts per second per volt - vco gain = lsbs per second per volt where: cs = 10 pf fs = 67 khz when r clk = 30 k ? c vco = 50 pf cs fs 1.1 c bw 1 1.25 r v c vco
6 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 general setup conditions ddc has external component selection software which consid- ers all the criteria below. in a simple fashion, it asks the key sys- tem parameters (carrier frequency, resolution, bandwidth, and tracking rate) needed to derive the external component values. the following recommendations should be considered when installing the rd-19230 r/d converter: 1) in setting the bandwidth (bw) and tracking rate (tr) (select- ing five external components), the system requirements need to be considered. for the greatest noise immunity, select the minimum bw and tr the system will allow. selecting a f bw that is too low relative to the maximum application tracking rate can create a spin-around condition in which the convert- er never settles. the relationship to insure against this condi- tion is detailed in table 2. 2) power supplies are 5 vdc. for lowest noise performance it is recommended that a 0.1 f or larger cap be connected from each supply to ground near the converter package. 3) resolver inputs and velocity output are referenced to agnd. this pin should be connected to gnd near the converter package. digital currents flowing through ground will not dis- turb the analog signals. 4) this device has several high impedance amplifier inputs (+c, -c, +s, -s, -vco, vel sj1, and vel sj2) that are sensi- tive to noise coupling. external components should be con- nected as close to the converter as possible. figure 5. -5v inverter connections 17 25 22 16 23 24 26 27 58 33 + + 10 f/10v v dd v dd v dd p pcap +5v ncap gnd agnd v ss p v ss * v ss rd-19230 47 f/10v * pin 16 has been renamed vss since it will typically be connected to -5 vdc. applications requiring a differential front-end configuration m ust connect this pin to vss. voltage follower mode can be implemented with pin 16 tied to vss by mak- ing external connections between the output of the sin/cos amplifiers and their respective inputs. when left unconnected, the rd-19230 will internally configure the front-end amplifiers in voltage follower mode. 5) setup of bandwidth and velocity scaling for the optimized crit- ically damped case should proceed as follows: as an example: calculate component values for a 16-bit converter with 100hz bandwidth, a tracking rate of 10 rps and a full scale velocity of 4 volts. 6) using the -5v inverter will eliminate the need for a -5 v sup- ply. refer to figure 5 for the necessary connections. when using the built-in -5 v inverter, the maximum tracking rate should be scaled for a full-scale velocity output of 3.5 v max. notes: 1) use of the -5 v inverter is not recommended for appli- cations that require the highest bw and tracking rates. 2) when using the rd-19230fx with the -5v inverter, the negative velocity output voltage should be limited to -3.5 volts. when performing tracking rate calculations this must be taken into consideration. - rv = = 97655 ? - compute c bw (pf) = = 21955 pf - compute r b = = 410 k ? 4 v 10 rps x 2 16 x 50 pf x 1.25 v 0.9 21955 x 10 -12 x 100 hz 3.2 x 67 khz x 10 8 97655 x 100 hz 2 - select the desired f bw (closed loop) based on overall system dynamics. - select f carrier 3.5f bw - select the applications tracking rate (in accordance with table 3), and use appropriate values for r set and r clk - compute rv = - compute c bw (pf) = - where fs = 67 khz for r clk = 30 k ? 100 khz for r clk = 20 k ? 125 khz for r clk = 15 k ? - compute r b = - compute 3.2 x fs (hz) x 10 8 rv x (f bw ) 2 full scale velocity voltage tracking rate (rps) x 2 resolution x 50 pf x 1.25 v 0.9 c bw x f bw c bw 10 table 2. tracking / bw relationship rps (max)/bw resolution 1 10 0.50 12 0.25 14 0.125 16
7 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 higher tracking rates and carrier frequencies maximum tracking rate is limited by the velocity voltage satura- tion (nominally 4 v) and the maximum internal clock rate (nomi- nally 1,333,333 hz for r clk = 30k). to achieve higher tracking rates, a higher internal counting rate must be programmed by setting rclk to a value less than 30k. see table 4 for the appropriate values. the rv resistor and an internal 50pf capacitor are configured as an integrating circuit that resets to zero after a count occurs in either direction. this circuit acts as a vco with velocity as its input and cb as its output. the rv resistor and an internal 50pf capacitor determine the maximum rate of the vco. rv must be chosen such that the maximum rate of the vco is less than the maximum internal clock rate. choose the tracking rate in accor- dance with table 3 to insure this relationship. the rates shown in table 3 are based on ~90% of the nominal internal clock rate. input transformers refer to table 5 to select the proper transformer for reference, synchro and resolver inputs. * 10 * 10 10 10 10 10 15k 20k 23k 23k 7 10 10 10 30k 23k 5 7 10 10 30k 30k** or open 16 14 12 10 resolution r clk ( ? ) r set ( ? ) table 4. carrier frequency (max) in khz * not recommended. ** the use of a high quality thin-film resistor will provide better temperature stability than leaving open. the relationship between the velocity voltage and the vco rate is given by: velocity voltage vco frequency 1 (rv x 50 pf x 1.25) = * ?0% frequency (hz) and line-to-line input voltage (vrms) tolerances ** 2 vrms output magnitudes are -2 vrms ?.5% full scale *** angle accuracy (max minutes) **** 3 vrms to ground or 6 vrms differential (?% full scale) dimensions are for each individual main and teaser 60 hz synchro transformers are active (requires ?5 vdc power supplies) 400 hz transformer temperature range: -55 c to +125 c 60 hz transformer temperature ranges: -55 c to +125 c, 0 to +70 c 3/6 **** 115 60 reference 24133 2 90 60 synchro 52039 3.4 115 400 reference b-426 2 90 400 r - r 52038 2 26 400 r - r 52037 2 11.8 400 r - r 52036 2 90 400 s - r 52035 2 11.8 400 s - r 52034 out (vrms)** in (vrms)* frequency (hz)* type p/n table 5. transformers 1.125 n/a 1.1 1 0.81 n/a 0.81 1 0.81 1 0.81 1 0.81 1 0.81 1 length (in) angle accuracy*** 1.125 1.14 0.61 0.61 0.61 0.61 0.61 0.61 width (in) .42 .42 0.32 0.3 0.3 0.3 0.3 0.3 height (in) 9 9 8 7 7 7 6 6 figure number table 3. max tracking rate (min) in rps r set ( ? ) r clk ( ? ) resolution 10 12 14 16 30k** or open 30k 1152 288 72 18 23k 20k 1728 432 108 27 23k 15k 2304 576 * * * not recommended. ** the use of a high quality thin-film resistor will provide better temperature stability than leaving open.
8 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 bottom view 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.115 max (2.92) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only terminals 0.025 ? 0.001 (6.35 ? 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b bottom view side view dimensions are shown in inches (mm). 1 5 3 6 10 11 15 16 20 t1a t1b synchro input resolver output -sin +sin -cos +cos s1 s3 s2 figure 7. transformer layout and schematic (resolver input - 52036/52037/52038) bottom view 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.115 max (2.92) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only terminals 0.025 ? 0.001 (6.35 ? 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b bottom view side view dimensions are shown in inches (mm). 1 3 6 10 11 15 16 20 t1a t1b resolver input resolver output -sin +sin -cos +cos s1 s3 s2 s4 figure 6. transformer layout and schematic (synchro input - 52034/52035)
9 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 1 5 6 10 input output bottom view 0.32 max (8.13) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 13 25 109876 terminals 0.025 ?.001 (6.35 ?.03) diam 0.125 (3.18) min length solder-plated brass t1a side view dimensions are shown in inches (mm). 0.105 (2.66) 0.600 (15.24) 0.81 max (20.57) 0.125 min (3.17) figure 8. transformer layout and schematic (reference input - b-426) b-426 1 5 6 10 rl rh s1 s3 s4 s2 1 3 6 10 11 15 20 16 external reference lo hi -s -r +r rd-19230 tib tia tia tib s1 s3 s2 52036(11.8v) 52037(26v) or 52038(90v) or 52034(11.8v) 52035(90v) or 1 3 10 6 16 11 15 20 5 +s +c gnd agnd cos or sin +s +c -c rl rh synchro input option resolver input option note: the external bw components as shown in figures 1 and 2 are necessary for the r/d to function. figure 10. typical transformer connections 1.14 max (28.96) case is black and non-conductive 1.14 max (28.96) * s1 * s3 (+15 v) +15 v (-r) +s + * * (rh) s2 (rl) + * (v) v (+r) +c (-vs) -vs 52039 or 24133 0.21 ?.3 (5.33 ?.76) 0.85 ?.010 (21.59 ?.25) 0.175 ?.010 (4.45 ?.25) noncumulative tolerance 0.040 ?.002 dia. pin. solder plated brass 0.42 (10.67) max. 0.25 (6.35) min. (bottom view) 0.13 ?.03 (3.30 ?.76) rh rl +15 v v (analog gnd) -vs (-15 v) output +r (rh) -r (rl) 24133 input s1 +15 v v (analog gnd) -vs (-15 v) output +s +c 52039 input s2 s3 the mechanical outline is the same for the synchro input trans- former (52039) and the reference input transformer (24133), except for the pins. pins for the reference transformer are shown in parenthesis ( ) below. an asterisk * indicates that the pin is omitted. figure 9. 60 hz synchro and reference transformer diagrams (synchro input - 52039 / reference input - 24133) typical inputs figures 10 through 14 illustrate typical input configurations.
10 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 r 1 r 3 r 2 r 4 external ref lo hi resolver s4 s3 s1 s2 +s -s sin cos -c +c a gnd rl rh notes: 1) resistors selected to limit vref peak to between 1.5 v and 4 v. 2) external reference lo is grounded, then r3 and r4 are not needed, and -r is connected to gnd. 3) 10k ohms, 1% series current limit resistors are recommended. see note 3. see note 3. gnd note: the external bw components as shown in figures 1 and 2 are necessary for the r/d to function. r 1 r 2 s3 s1 s2 +s -s sin cos -c +c a gnd s4 r 1 r 2 gnd r 2 r 1 + r 2 2 x volt = r 1 + r 2 should not load the resolver; it is recommended to use a r 2 = 10 k ? r 1 + r 2 ratio erros will result in angular errors, 2 cycle, 0.1% ratio error = 0.029? peak error. note: the external bw components as shown in figures 1 and 2 are necessary for the r/d to function. figure 11. typical connections, 2 v resolver, direct input figure 12. typical connections, x- volt resolver, direct input
11 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 r i s1 s3 +s -s sin r f r i r f r i s4 s2 +c -c r f r i r f cos a gnd converter 810 12 15 13 2 3 1 6 16 7 4 5 - + - + resolver input s1 and s3, s2 and s4, and rh and rl should be ideally twisted shielded, with the shield tied to gnd at the converter. for ddc-49530: r i = 70.8 k ? , 11.8 v input, synchro or resolver. for ddc-49590: r i = 270 k ? , 90 volt input, synchro or resolver. maximum additional error is 1 minute. when using discrete resistors: resolver l-l voltage = x 2 vrms, where r f 6 k ? r i r f note: the external bw components as shown in figures 1 and 2 are necessary for the r/d to function. figure 13. differential resolver input, using ddc-49530 (11.8 v) or ddc-49590 (90 v), or (2 v) direct using discrete resistors r i s1 s3 +s -s sin r f r i r f r i s2 +c -c r /2 i cos a gnd converter 8 15 11 15 14 2 3 1 6 16 7 4 5 r i 9 r / 3 f r / 3 f 10 - + - + s1, s2, s3 should be triple twisted shielded; rh and rl should be twisted shielded; in both cases the shield should be tied to gnd at the converter. 11.8 volt input = ddc-49530: r i = 70.8 k ? , 11.8 v input, synchro or resolver. 90 volt input = ddc-49590: r i = 270 k ? , 90 volt input, synchro or resolver. maximum additional error is 1 minute. when using discrete resistors: resolver l-l voltage = x 2 vrms, where r f 6 k ? r i r f synchro input note: the external bw components as shown in figures 1 and 2 are necessary for the r/d to function. figure 14. synchro input, using ddc-49530 (11.8 v) or ddc-49590 (90 v)
12 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 2 1 -vco vel +5 v -5 v 100 k ? (offset) 100 r v 0.8 r v 0.4 r (scaling) v rd-19230 figure 15. velocity trimming up /dn the up /dn input selects the gain of the amplifier driving the de- selected set of bandwidth components. up /dn has three input states. see table 6 to relate input to gain. benefit of switching resolution on the fly switching resolution on the fly can be used in applications that require high resolution for accurate position control, and tracking rates or settling times that are faster than the high resolution mode will allow. the rd-19230 can track four times faster for each step down in resolution (i.e., a step from 16 bits to 14 bits). the velocity out- put will be scaled down by a factor of four with each step down in resolution. for example, if the velocity output is scaled such that 4 volts = 10 rps in 16 bit resolution, then the same con- verter will output 1 volt for 10 rps in 14 bit resolution. to avoid glitches in the velocity output, the second set of bandwidth com- ponents can be pre-charged to the expected voltage, and switched in using the shift input at the same time the resolu- tion is changed. this will allow for a smooth velocity transition, resulting in reduced errors and minimal settling time after the change. figure 17 shows the way the converter behaves during a change in resolution while tracking at a constant velocity. the first illustration shows the benefits of switching in pre-charged components while changing resolution. the second illustration shows the result without the benefits of switching on the fly. the signals that have been recorded are: 1) vel: velocity output pin on the rd-19230 2) error: this is the analog representation of the error between the input and the output of the rd-19230 3) d0: an input resolution control line to the rd-19230 4) bit : built-in-test output pin of the rd-19230 dc inputs as noted in table 1, the rd-19230 will accept dc inputs. it is necessary to set the ref input to dc by tying rh to +5 v and rl to gnd or -5 \/. velocity trimming rd-19230 specifications for velocity scaling, reversal error, and offset are listed in table 1. velocity scaling and offset are exter- nally trimmable for applications requiring tighter specifications than those available from the standard unit. figure 15 shows the setup for trimming these parameters with external pots. it should also be noted that when the resolution is changed, vel scaling is also changed. optional bandwidth components the rd-19230 provides the option of using a second set of bandwidth components. the second set of components can be used for switch-on-the-fly or dual-bandwidth applications. the shift and up /dn inputs are used when switching bandwidth components, and their operation is described below. refer to the block diagram, figure 1. shift the shift pin is an input that chooses between the vel1 and vel2 bandwidth components. this pin has an internal pull-up to +5v. when the shift pin is left open, or a logic 1 is applied, the vel1 components are selected. when a logic 0 is applied, the vel2 components are selected. the deselected set of band- width components are driven by an amplifier, with programmable gain, that follows the velocity amplifier. this amplifier can be used to pre-charge the deselected set of components to the volt- age level that is expected after a change in resolution. (see description on benefit of switching resolution on the fly.) table 6. precharge amplifier gain programming up/dn logic 1 4 logic 0 1/4 -5 v 1 gain resolution increase resolution decrease dual bandwidth function
13 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 figure 17. benefit of switching resolution on the fly without switch resolution on the fly implemented when this system uses the switch resolution on the fly imple- mentation, the velocity signal immediately assumes the pre- charged level of the second set of components, resulting in small errors and reduced settling times. notice that the bit output, in figure 17, does not indicate a fault condition. when this system type does not use the switch resolution on the fly implementation, large errors and increased settling times result. the errors exceed 100 lsbs causing the bit to flag for a fault condition. switch on the fly implementation the following steps detail switching resolution on the fly. 1) the shift pin should be controlled synchronously with the change in resolution. when shift is logic high, the vel1 com- ponents will be selected. when shift is logic 0, the vel2 com- ponents will be selected. 2) the second set of bw components (c bw2 , r b2 , c bw2/10 ) should typically be of the same value as the first set (c bw1 , r b1 , c bw1/10 ,) and should be installed on vel 2 and vel sj 2 . note: each set of bandwidth components must be chosen to insure that the tracking rate to bw ratio (listed in table 2) is not exceeded for the resolution in which it will be used. 3) up /dn will program the direction of the gain. if the resolution is increasing (up /dn logic 0), the gain of the pre-charge amplifier should be set to four. if the resolution is decreasing (up /dn logic 1), the gain should be set to 1/4. the gain of the pre-charge amplifier should be programmed prior to switching the resolution of the converter, allowing enough time for the components to settle to the pre-charged level. this time will depend on the time constant of the bandwidth components being charged. if switching is limited to two adjacent resolu- tions (i.e., 14 and 16) then the pre-charge amplifier can be set with switch resolution on the fly implemented 27 58 +5v up/dn shift rd-19230 d1 d0 figure 16. input wiring - switching on the fly between 14 and 16 bit resolution up to continuously maintain the appropriate velocity voltage on the deselected components, resulting in the fastest possi- ble switching times. see figure 16 for an example of the input wiring connections necessary for switching on the fly between 14 and 16 bit resolution. dual bandwidths with the second set of bw component pins, the user can set two bandwidths for the rd-19230 and choose between them. to use two bandwidths, proceed as follows: 1) tie up /dn to pin -5v. 2) choose the two bandwidths following the guidelines in the general setup considerations; the r v resistor must be the same value for both bandwidths. 3) use the shift pin to choose between bandwidths. a logic 1 selects the vel1 components and a logic 0 selects the vel2 components. vel 0v -5v error 0 ? d0 0v 5v bit 0v 5v error = 13.6 lsbs per box vel 0v -5v error 0 ? d0 0v 5v bit 0v 5v error = 1500 lsbs per box
14 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 data data valid 150 nsec max inhibit 100 nsec max enable 150 nsec max data data valid high z high z 250 to 750 nsec cb 50 nsec data data valid data valid figure 18. inhibit timing figure 19. enable timing figure 20. converter busy timing inhibit, enable, and cb timing the inhibit (inh ) signal is used to freeze the digital output angle in the transparent output data latch while data is being trans- ferred. application of an inhibit signal does not interfere with the continuous tracking of the converter. as shown in figure 18, angular output data is valid 150 ns maximum after the applica- tion of the negative inhibit pulse. output angle data is enabled onto the tri-state data bus in two bytes. enable msbs (em ) is used for the most significant 8 bits and enable lsbs (el ) is used for the least significant 8 bits. as shown in figure 19, output data is valid 150 ns maximum after the application of a negative enable pulse. the tri-state data bus returns to the high impedance state 100 ns maximum after the rising edge of the enable signal. the converter busy (cb) signal indicates that the tracking con- verter output angle is changing 1 lsb. as shown in figure 20, output data is valid 50 ns maximum after the middle of the cb pulse. cb pulse width is 1/40 f s , which is nominally 375 ns. tion of the parallel data outputs may be changed any time after the encoder resolution is latched (see figure 23). note: the encoder resolution must be less than or equal to the resolution of the parallel data outputs. refer to figure 21. the timing of the a, b and zip (or north reference pole [nrp]) output is dependent on the rate of change of the synchro/resolver position (rps or degrees per second) and the encoder resolution latched into the rd-19230 (refer to figure 22). the calculations for the timing are: n = encoder resolution latched into rd-19230 t = 1 / ( 2 n * velocity(rps)) t = 1 / ( velocity(rps)) clarification of a_q u ad_b , u/b and zip_en functions the rd-19230 is a tracking converter which is designed with a type ii closed servo loop. the type ii closed servo loop has an internal incremental integrator. this integrator acts as an up- down position counter. an ac error (e) within the rd-19230 rep- resents the difference between (current angle to be digitized) and (the angle stored in digital form in the up-down counter). because the rd-19230 constitutes in itself a type ii closed loop servomechanism, it continuously attempts to null the error to zero. this is accomplished by counting up or down 1 lsb until is equal to thus having an error of zero. when a_q u ad_b is logic 0, encoder emulation mode is select- ed (i.e. the u/b output [pin 29] is programmed to b). the encoder emulator resolution is set on the falling edge of a_q u ad_b (see table 7). when a_q u ad_b is logic 1, encoder emulation mode is not selected (i.e. the u/b output is set to u, which indicates the direction of the internal position counter). table 8. zip_en (pin 55) function zip_en (pin 55) cb/zi (pin 31) 0 zi 1 cb table 7. a_q u ad_b (pin 30) function a_q u ad_b (pin 30) u/b (pin 29) 0 b 1 u internal encoder emulation the rd-19230 can be programmed to encoder emulation mode by connecting the a_q u ad_b input to gnd. the u/b output pin becomes b (lsb xor lsb + 1). the a (lsb + 1) and b output signals can be used in control systems that are designed to inter- face with incremental optical encoders. to enable the zero index pulse, zip_en should be tied to gnd. the resolution of the incremental outputs is latched from the d0 and d1 inputs on the low going edge of a_q u ad_b . the resolu-
15 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 note: u indicates the direction of the counter. it stands for ?up?. if the rd-19230 is at a static angle awaiting a new angle , u indicates the direction the counter was going to get to the current angle . as the error is approaching zero, the internal analog circuitry voltage may over shoot before settling - which would then indicate an incorrect direction. because of this over shoot, the u output should not be relied on after set- tling to a static state. only during active resolver movement will the u output state be reliable. u is a logic 1 when going in the positive direction (increas- ing angle). it is a logic 0 when going in the negative direction (decreasing angle). this is the same as it is in the rdc-19220. zip_en chooses between the cb and zero index pulse outputs and is independent of encoder emulation mode. a logic 1 enables the cb pulse, a logic 0 enables the zero index pulse (see table 8). note: when the rd-19230fx is set for 16-bit mode, the lsb is bit 16. when the rd-19230fx is set for 14-bit mode, the lsb is bit 14 and bits 15 and 16 are set to logic ?0?. (see table 1, note 1). synthesized reference the synthesized reference section of the rd-19230 eliminates errors due to phase shift between the reference and signal inputs. quadrature voltages in a resolver or synchro are by def- inition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. due to the inductive nature of syn- chros and resolvers, their output signals lead the reference input signal (rh and rl). when an uncompensated reference signal is used to demodulate the control transformer s output, quadra- ture voltages are not completely eliminated. as shown in the block diagram, figure 1, the converter synthesizes its own internal reference signal based on the sin and cos signal inputs. therefore, the phase of the synthesized (internal) refer- ence is determined by the signal input, resulting in reduced quadrature errors. built-in-test (bit ) the bit output is active low, and is triggered if any of the follow- ing conditions exist: 1) loss of signal (los) - sin and cos inputs both less than 500mv. 2) loss of reference (lor) - reference input less than 500 mv. 3) excessive error - this error is detected by monitoring the demodulator output, which is proportional to the difference between the analog input and digital output. when it exceeds approximately 100 lsbs (in the selected resolution), bit will be asserted. this condition can occur any time the analog input changes at a rate in excess of the maximum tracking rate. during power up, the converter may see a large differ- ence between the sin/cos inputs and the digital output angle held in its counter. bit will be asserted until the converter set- tles within ~ 100 lsb s of the final result. 4) 180 phase error input signal to reference input (false null) causes a bit plus kickstarts the converter counter to correct the error. the los has a filter on it to filter out the reference. since the lowest specified reference frequency is 47 hz (~27 ms), the figure 22. incremental encoder emulation 2t b(x- or lsb & lsb+1) a (lsb+1) zip (nrp) 359.95 0 t t data valid 50 nsec d0/d1 a quad b figure 23. timing for incremental encoder emulation resolution control rd-19230 1 msb 2 3 4 9 10 11 12 13 14 15 bit 16 lsb b 1 0 1 2 1 4 1 6 a 5 6 7 8 figure 21. incremental encoder emulation resolution control
16 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 filter must have a time constant long enough to filter this out. time constants of 50 ms or more are possible. a 500 s dynamic delay occurs before the error bit becomes active. this dynamic delay is responsive to the active filter loop. lvdt mode as shown in table 1, the rd-19230 unit can be made to oper- ate as an lvdt-to-digital converter. in this mode the rd-19230 functions as a ratiometric tracking linear converter. when linear ac inputs are applied from a lvdt the converter operates over one quarter of its range. this results in two less bits of resolution for lvdt mode than are provided in resolver mode. ldvt output signals need to be scaled to be compatible with the converter input. figure 25 is a schematic of an input scaling circuit applicable to 3-wire lvdts. the value of the scaling con- stant a is selected to provide an input of 2 vrms at full stroke of the lvdt. the value of scaling constant b is selected to provide an input of 1 vrms at null of the lvdt. suggested components for implementing the input scaling circuit are a quad op-amp, +s -s sin ar r +c -c cos r - + - + r r r ar c 1 br 2r 2r r br +rh -rl r c 2 2 wire lvdt ref in r 2 v fs = 2 v figure 24. 2-wire lvdt direct input table 9. 12-bit lvdt output code for figure 25 lvdt output msb lsb + over full travel + full travel -1 lsb +0.5 travel +1 lsb null - 1 lsb -0.5 travel - full travel - over full travel 01 xxxx xxxx xxxx 00 1111 1111 1111 00 1100 0000 0000 00 1000 0000 0001 00 1000 0000 0000 00 0111 1111 1111 00 0100 0000 0000 00 0000 0000 0000 11 xxxx xxxx xxxx c 1 = c 2 , set for phase lag = phase lead through the lvdt. such as a op11 type, and precision thin-film resistors of 0.1% tolerance. figure 24 illustrates a 2-wire lvdt configuration. data output of the rd-19230 is binary coded in lvdt mode. the most negative stroke of the lvdt is represented by all zeros and the most positive stroke of the lvdt is represented by all ones. the most significant 2 bits (2 msbs) may be used as over- range indicators. positive overrange is indicated by code 01 and negative overrange is indicated by code 11 (see table 9).
17 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 +s -s sin ar r +c -c cos r' - + - + r/2 r r ar br 2r' 2r' r' br +rh -rl r' r' r v b v a v b v a lvdt output +fs -fs null cos sin rdc-19230 input -fs +fs null 1v 2v 1 1 b = = v a null v b null 2 a = (v a - v b ) max a sin = 1+ (v a - v b ) 2 a cos = 1- (v a - v b ) 2 figure 25. 3-wire lvdt scaling circuit notes: 1. r' 10 k ? 2. consideration for the value of r is lvdt loading.
18 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 figure 26. rd-19230 mechanical outline rl bit 1 64 32 bit 15 vss (-5v) 48 16 rh cb (zi) 63 31 bit 7 -s 47 15 inh a_q u ad_b 62 30 bit 14 sin 46 14 d1 u/b 61 29 bit 6 +s 45 13 d0 bit 60 28 bit 13 -c 44 12 up /dn vddp 59 27 bit 5 cos 43 11 vdd (+5v) pcap 58 26 bit 12 +c 42 10 enl gnd 57 25 n/c tp2 (test point) 41 9 tp6 (test point) ncap 56 24 bit 4 vel1 40 8 zip_en vssp 55 23 bit 11 tp1 (test point) 39 7 tp5 (test point) agnd 54 22 bit 3 vel2 38 6 n/c enm 53 21 bit 10 shift 37 5 tp4 (test point) r set 52 20 bit 2 sj2 36 4 a (lsb + 1) r clk 51 19 bit 9 sj1 35 3 bit 16 tp3 (test point) 50 18 n/c -vco 34 2 bit 8 vss (-5v) 49 17 vdd (+5v) vel 33 1 table 10. rd-19230 pinouts name name # # name name # # notes: 1. see figure 5 for +5 v only operation. 0.5200.010 (13.20.25) 0.3940.004 (10.000.10) 0.3940.004 (10.000.10) 0.5200.010 (13.20.25) 0.078+0.004 2.00+0.10 0.0098min,0.0197max (0.25min,0.50max) 0.0197 (0.50) 0.096max (2.45max) 0.008 (0.22) 0.035+0.006 0.88+0.15 0.007max (0.17max) 0.096max (2.45max) 0.0098min,0.0197max (0.25min,0.50max) -0.002 -0.05 -0.004 -0.10 64 49 pin1 32 17 16 ( ( ) ) 48 33 dimensions shown are in inches (millimeters) rd-19230fx -xxx date code
19 data device corporation www.ddc-web.com rd-19230 rev. f-11/01-250 ddc-49530, ddc-57470 resistor values (11.8 v inputs) table 11. front-end thin-film resistor networks(see figure 28) symbol abs value tol (%) rel to rel value tol (%) tcr(ppm) r1 70.8 k 0.1 25 r2 r3 r1 r4 12 k 12 k 0.02 0.02 2 2 r4 r1 70.8 k 0.02 2 r5 r1 70.8 k 0.02 2 r6 r1 35.4 k 0.02 2 r7 r6 6.9282 k 0.02 2 r8 r6 5.0718 k 0.02 2 r9 r11 5.0718 0.02 2 r10 r11 6.9282 k 0.02 2 r11 r1 70.8 k 0.02 2 ddc-49590 resistor values (90 v inputs) r1 270 k 0.1 25 r2 r1 6 k 0.02 2 r3 r4 6 k 0.02 2 r4 r1 270 k 0.02 2 r5 r1 270 k 0.02 2 r6 r1 135 k 0.02 2 r7 r6 3.4641 k 0.02 2 r8 r6 2.5359 k 0.02 2 r9 r11 2.5359 k 0.02 2 r10 r11 3.4641 k 0.02 2 r11 r1 270 k 0.02 2 0.870 max (22.10) 0.250 0.005 (6.35 0.13) dimensions shown are in inches (mm). +0.025 0.325 -0.015 +0.64 (8.26 ) -0.38 0.13 0.005 (3.30 0.13) 0.020 min (0.51) 0.125 min (3.18) 0.075 0.015 (1.91 0.38) 0.018 0.003 (0.46 0.08) 0.100 typ (2.54) 0.320 - 0.300 (8.13 - 7.62) 0.015 0.009 (0.38 0.23) r11 r10 r9 16 15 14 13 r8 r7 r6 12 11 10 9 r1 r2 12 3 r5 78 r3 r4 45 6 figure 29. 16-pin thin-film resistor network dip mechanical outline (ddc-49530, ddc-49590, ddc-55688) figure 28. (ddc-49530, ddc-49590, ddc-57470) layout and resistor values (see table 11) figure 30. 16-pin thin-film resistor network flat-pack mechanical outline (ddc-57470) .405 0.299 (7.6) dimensions shown are in inches (mm). 0.406 (10.3) 0.014 (.36) 0.342 (8.7) 7 ? 45 ? 0.101 (2.6) 0.092 (2.3) 0.009 (0.23) 0.016 (0.40) 0.050 (1.27) 16 15 14 13 12 11 10 9 12 3 r2 78 r1 45 6 figure 27. (ddc-55688) layout and resistor values (r1 and r2 = 10 k ? 1.0% tol, absolute tc = 100 ppm max)
20 f-11/01-250 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7382 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u ordering information rd-19230fx-x x x x supplemental process requirements: t = tape and reel (50 pc. min. order) accuracy: 2 = 4 min + 1 lsb 3 = 2 min + 1 lsb reliability: 0 = standard ddc procedures operating temperature range: 2 = -40 to +85 c 3 = 0 to +70 c thin-film resistor networks: ddc-49530 = 11.8 v inputs, dip package ddc-57470 = 11.8 v inputs, flat-pack package ddc-49590 = 90 v inputs, dip package ddc-55688 = 2 v direct, dip package component selection software: component selection software can be downloaded from our website ( www.ddc-web.com )

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